Integrated circuits are used in a variety of environments including harsh ones that can seriously deter the integrated circuit's proper operation. In general, the phenomena known as electrostatic discharge (ESD) and electrical overstress (EOS) can affect and, in some cases, prohibit the functioning of integrated circuits. ESD may be thought of as high-energy pulse that occurs whenever someone or something carrying an electrical charge touches the integrated circuit. In EOS, a voltage spike of a longer duration exists. An example of EOS occurs when a system is improperly tested or during improper operation of an electrical system that causes a large voltage spike to enter the integrated circuit. In some even harsher environments, such as that of an automobile, a phenomenon known as "load dump" may occur. An example of the load dump electrical transient happens when a battery cable disconnects from the battery terminal as a result of the car hitting a bump or experiencing some other jolt. The disconnected battery cable, if connected to the alternator, may contact a component such as an engine control circuit that has an embedded integrated circuit. This battery cable contact dumps the energy from the alternator into the integrated circuit and can destroy its proper operation.
Integrated circuits that protect against ESD often use on-chip protection at the input and output pins. Protection devices that protect against ESD may protect against high-energy pulses of up to 15 killivolts. On-chip protection device designs for pulses having magnitudes beyond this level are not possible due to practical limits of size on the integrated circuit chip. Circuits that address the EOS and load dump situations may use a metal oxide veristor (MOV) device to absorb the high-energy pulse. MOV devices, however, are bulky and expensive to implement for all integrated circuits that may require protection. The heat that the known protection devices produces also impairs performance of integrate circuits as the temperature rises in the associated silicon substrate region.